The present invention relates to a process for manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device technique and, more particularly, to a technique which is effective when applied to the process for manufacturing a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory) and a semiconductor integrated circuit device technique.
The DRAM has a memory cell comprising one memory cell selecting MIS transistor and a capacitor connected in series with the MIS transistor so that its degree of integration is high enough to lower the unit price per bit. Therefore, DRAMs are widely used in main memories for various computers or communication devices that require a memory of high storage capacity.
The memory capacity of the DRAM has a tendency to increase more and more. In accordance with this tendency, the area occupied by the memory cell tends to decrease with a view to improving the degree of integration of the memory cells of the DRAM.
However, the capacitance of the information storage capacitive element (capacitor) in a memory cell of a DRAM is required to be a certain value from the standpoint of considering the operation margin, soft errors and so on, independently of the DRAM generation, and cannot be proportionally reduced, as generally known in the art.
Thus, the capacitor structure has been developed to have a necessary capacitance in a limited small occupation area. In one of the results of these developments a three-dimensional capacitor structure such as the so-called xe2x80x9cstacked capacitorxe2x80x9d, in which two layers of capacitor electrodes are stacked through a capacitor insulation film is adopted.
The stacked capacitor generally has a structure in which the capacitor electrodes are arranged over a memory cell selecting MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and represented by a cylindrical or fin type capacitor structure. Either of these is characterized in that a large capacitance can be ensured by increasing the size in the height direction of the capacitor but without increasing the size in the widthwise direction of the capacitor.
A DRAM having memory cells is disclosed in Japanese Patent Laid-Open No. 122654/1995 relating to the so-called xe2x80x9cCapacitor Over Bitline (will be abbreviated to COB)xe2x80x9d in which the information storage capacitive elements are provided in a layer over bit lines.
We have found out the following problems in the above-specified technique.
Specifically, the connection hole for electrically connecting different wiring layers or a wiring line and a semiconductor substrate has a such a high aspect ratio as to make it difficult to open a connection hole and to fill it in with a conductor layer. This problem is serious in the case of the connection hole portion for connecting the upper wiring layer and the lower wiring layer in the stacked capacitor especially when the information storage capacitive element of the DRAM is a stacked capacitor. This is caused by the deepened connection hole because the capacitance of the capacitor is increased without increasing the occupation area.
We have studied the prior art from the view point of the wiring structure of the DRAM and have found PCT Laid-Open No. 9719468, for example, on that technique. This Laid-Open discloses the structure in which three buried wiring layers are interposed between the capacitor and the semiconductor substrate of the DRAM. Also disclosed is a structure in which multiple plugs are stacked, but there is no mention of the structure in which the lines buried in the layer common to the bit lines are led out through the stacked plugs to the wiring layer over the capacitor.
An object of the invention is to provide a technique capable of facilitating the works to open a connection hole for connecting different wiring layers and to fill in the connection hole with a conductor film.
The above-specified and other objects and the novel features of the invention will become apparent from the following description to be made with reference to the accompanying drawings.
Representative aspects of the invention to be disclosed herein will be briefly described in the following.
According to the invention, there is provided a process for manufacturing a semiconductor integrated circuit device including on a semiconductor substrate a plurality of memory cells each having a memory cell selecting transistor and an information storage capacitive element connected in series with the memory cell selecting transistor, comprising forming a bit line and a first line in the same wiring layer over the semiconductor substrate; forming the information storage capacitive element over the bit line not through another wiring layer line; and forming a second line over the information storage capacitive element, wherein the process further comprises forming between the first line and the second line a first connection portion electrically connected in direct contact with the first line, and a second connection portion electrically connected in direct contact with the first connection portion.
In a semiconductor integrated circuit device manufacturing process according to the invention, moreover, the second connection portion has a planar size larger than that of the first connection portion.
In a semiconductor integrated circuit device manufacturing process of the invention, moreover, the second connection portion has a planar size larger than that of the first connection portion to an extent that it includes a plurality of the first connection portions.
According to the invention, there is further provided a process for manufacturing a semiconductor integrated circuit device including on a semiconductor substrate a plurality of memory cells each having a memory cell selecting transistor and an information storage capacitive element connected in series with the memory cell selecting transistor, comprising:
(a) forming a bit line and a first line in the same wiring layer over said semiconductor substrate;
(b) forming over said semiconductor substrate a first insulation film covering the bit line and the first line;
(c) opening in the first insulation film a first connection hole for exposing the first line in the region other than the region where the memory cell is formed;
(d) forming the first connection portion by filling it in with a first conductor film;
(e) forming a second insulation film made of a material allowing a relatively high etching selection ratio for the first insulation film in such a way as to cover the upper faces of the first insulation film and the first connection portion;
(f) forming the information storage capacitive element over the bit line in said memory cell forming region;
(g) opening a second connection hole for exposing the first connection portion in the region other than the region where the memory cell is formed in the second insulation film formed between the wiring layer over the information storage capacitive element and the first connection portion, and in a third insulation film made of such a material to allow a relatively high etching selection ratio for the second insulation film; and
(h) forming a second connection portion electrically connected in direct contact with the first connection portion, by burying a second conductor film in the second connection hole.
According to the invention, moreover, there is further provided a process for manufacturing a semiconductor integrated circuit device including on a semiconductor substrate a plurality of memory cells each having a memory cell selecting transistor and an information storage capacitive element connected in series with the memory cell selecting transistor, comprising:
(a) forming a bit line and a first line in the same wiring layer over the semiconductor substrate;
(b) forming over the semiconductor substrate a first insulation film covering the bit line and the first line;
(c) opening in the first insulation film a first connection hole for exposing the first line in the region other than the region where the memory cell is formed;
(d) forming the first connection portion by filling it in with a first conductor film;
(e) forming the information storage capacitive element over the bit line in the memory cell forming region;
(f) opening a second connection hole for exposing the first connection portion in the region other than said memory cell forming region in the insulation film formed between the wiring layer over the information storage capacitive element and the first connection portion; and
(g) forming a second connection portion electrically connected in direct contact with said first connection portion, by burying the second conductor film in the second connection hole.
According to the invention, there is further provided a process for manufacturing a semiconductor integrated circuit device including on a semiconductor substrate a plurality of memory cells each having a memory cell selecting transistor and an information storage capacitive element connected in series with the memory cell selecting transistor, comprising:
(a) forming a bit line and a first line in the same wiring layer over the semiconductor substrate;
(b) forming over the semiconductor substrate a first insulation film covering the bit line and the first line;
(c) opening in the first insulation film a first connection hole for exposing the first line in the region other than the region where the memory cell is formed, and opening a connection hole for the information storage capacitive element for exposing the bit line in the memory cell forming region;
(d) forming a first connection portion and a connection portion for an information storage capacitive element by filling in the first connection hole and the information storage capacitive element connection hole with a first conductor film;
(e) forming a second insulation film made of a material allowing a relatively high etching selection ratio for the first insulation film in such a way as to cover the upper faces of the first insulation film, the first connection portion and the information storage capacitive element connection portion;
(f) forming the information storage capacitive element over the bit line in the memory cell forming region;
(g) opening a second connection hole for exposing the first connection portion in the region other than the memory cell forming region in the second insulation film formed between the wiring layer over the information storage capacitive element and the first connection portion, and in a third insulation film made of a material to allow a relatively high etching selection ratio for the second insulation film; and
(h) forming a second connection portion electrically connected in direct contact with the first connection portion, by burying a second conductor film in the second connection hole.
According to the invention, there is further provided a process for manufacturing a semiconductor integrated circuit device including on a semiconductor substrate a plurality of memory cells each having a memory cell selecting transistor and an information storage capacitive element connected in series with the memory cell selecting transistor, comprising:
(a) forming a bit line and a first line in the same wiring layer over the semiconductor substrate;
(b) forming over the semiconductor substrate a first insulation film covering the bit line and the first line;
(c) forming over the first insulation film a second insulation film made of a material allowing a relatively high etching selection ratio for the first insulation film;
(d) forming the information storage capacitive element over the bit line in the region where the memory cell is formed;
(e) opening a connection hole between wiring layers, through which the first line is exposed, in the region other than the memory cell forming region, in a first insulation film and a second insulation film formed between the wiring layer over the information storage capacitive element and the first line, and in a third insulation film formed over the first insulation film and the second insulation film and made of a material allowing a relatively high etching selection ratio for the second insulation film; and
(f) forming a connection portion between the wiring layers electrically connected in direct contact with the first line, by filling in the connection hole between the wiring layers with a conductor film,
wherein the step of forming the connection hole between the wiring layers includes
forming a mask pattern for forming a connection hole over the third insulation film;
performing a first etching process to open a first hole for exposing a part of the second insulation film in the third insulation film exposed from the mask pattern, by etching using the mask pattern as an etching mask, under the condition in which the third insulation film is etched off more easily than the second insulation film at a relatively increased etching selection ratio between the second insulation film and the third insulation film;
performing, after the first etching process step, a second etching process to remove the second insulation film exposed from the bottom portion of the first hole and to open a second hole for exposing a part of the first insulation film in the second insulation film, by etching using the mask pattern as an etching mask under the condition in which the second insulation film is etched off more easily than the third insulation film at a relatively increased etching selection ratio between the second insulation film and the third insulation film; and
performing, after the second etching process step, a third etching process to remove the first insulation film exposed from the bottom of the second hole and to open the connection hole between the wiring layers for exposing the first insulation film, by etching under the condition in which the first insulation film is etched off more easily than the second insulation film at a relatively increased etching selection ratio between the second insulation film and the first insulation film.
In the semiconductor integrated circuit device manufacturing process, according to the invention,
wherein the step (d) includes forming a first electrode constituting the information storage capacitive element; forming a capacitor insulation film on the surface of the first electrode; and forming a second electrode covering the capacitor insulation film,
wherein the step (e) includes opening a connection hole extending through the second electrode for leading out the second electrode in the third insulation film,
wherein the step of forming the connection hole between the wiring layers and the connection hole for leading out the second electrode includes
forming a mask pattern over the third insulation film;
performing a first etching process to open a first hole constituting the connection hole between the wiring layers and for exposing a part of the second insulation film, and to open a first hole which constitutes the connection hole for leading out the second electrode and extends through the second electrode and the bottom of which extends to an intermediate position of the third insulation film, in the third insulation film exposed from the mask pattern, by etching using the mask pattern as an etching mask under the condition in which the third insulation film is etched off more easily than the second insulation film at a relatively increased etching selection ratio between the second insulation film and the third insulation film;
performing, after the first etching process step, a second etching process to remove the second insulation film exposed from the bottom of the first hole for the connection hole between the wiring layers and to open a second hole for the connection hole between the wiring layers and for exposing a part of the first insulation film, by etching using the mask pattern as an etching mask under the condition in which the second insulation film is etched off more easily than the third insulation film at a relatively increased etching selection ratio between the second insulation film and the third insulation film; and
performing, after the second etching process step, a third etching process to open a connection hole between the wiring layers for exposing the first insulation film from the bottom of the second hole for the connection hole of the insulation film between the wiring layers, by etching under the condition in which the first insulation film is etched off more easily than the second insulation film at a relatively increased etching selection ratio between the second insulation film and the first insulation film, and
wherein said (f) step includes burying a conductor film in the connection hole between the wiring layer and in the second electrode lead-out connection hole, and forming the connection portion between the wiring layers electrically connected in direct contact with the first line, and the second electrode lead-out connection portion electrically connected with the second electrode.
According to the invention, there is further provided a process for manufacturing a semiconductor integrated circuit device, in which a memory cell including a first MISFET and a capacitive element connected in series with the first MISFET is formed in a first region of a semiconductor substrate and in which a second MISFET is formed in a second region of the semiconductor substrate, comprising:
(a) forming a first line in the second region of the semiconductor substrate;
(b) forming a first insulation film over the first line;
(c) forming a first opening in the first insulation film to expose a portion of the first line;
(d) forming a first conductor layer selectively in the opening;
(e) forming a second insulation film over the first insulation film and the first conductor layer;
(f) forming a third insulation film over the second insulation film;
(g) forming a second opening in the third insulation film in the first region;
(h) forming a second conductor layer selectively along the inner wall of the second opening;
(i) forming a fourth insulation film and a third conductor layer over the second conductor layer;
(j) forming a third opening in the third insulation film and the second insulation film in the second region in such a way as to expose a part of the first conductor layer; and
(k) forming a fourth conductor layer in the third opening,
wherein at the second opening forming step, the third insulation film is etched under the condition in which the etching rate of the third insulation film is higher than that of the second insulation film, and
wherein at the third opening forming step, the third insulation film is etched under the condition in which the etching rate of the third insulation film is higher than that of the second insulation film, and then the second insulation film is etched under the condition in which the etching rate of the second insulation film is higher than that of the third insulation film.
According to the invention, there is further provided a process for manufacturing a semiconductor integrated circuit device, in which a memory cell including a first MISFET and a capacitive element connected in series with the first MISFET is formed in a first region of a semiconductor substrate and in which a second MISFET is formed in a second region of the semiconductor substrate, comprising:
(a) forming a first line in the second region of the semiconductor substrate;
(b) forming a first insulation film over the first line;
(c) forming a second insulation film over the first insulation film;
(d) forming a third insulation film over the second insulation film;
(e) forming a second opening in the third insulation film in the first region;
(f) forming a first conductor layer selectively along the inner wall of the second opening;
(g) forming a fourth insulation film and a second conductor layer over the first conductor layer;
(h) forming a third opening in the third insulation film and the second insulation film in the second region in such a way as to expose a part of the first conductor layer; and
(i) forming a third conductor layer in the third opening,
wherein at the second opening forming step, the third insulation film is etched under the condition in which the etching rate of the third insulation film is higher than that of the second insulation film, and
wherein at the third opening forming step, the third insulation film is etched under the condition in which the etching rate of the third insulation film is higher than that of the second insulation film, then the second insulation film is etched under the condition in which the etching rate of the second insulation film is higher than that of the first insulation film, and the first insulation film is etched in such a way as to expose a part of the first line.